Abstract: [No abstract available]

Abstract: Stencil computation represents an important numerical kernel in scientific computing. Leveraging multicore or manycore parallelism to optimize such operations represents a major challenge due both to the bandwidth demand and the low arithmetic intensity. The situation is worsened by the complexity of current architectures and the potential impact of various mechanisms (cache memory, vectorization, compilation). In this paper, we describe a multi-level optimization strategy that combines manual vectorization, space tiling and stencil composition. A major effort of this study is the comparison of our results with Pochoir stencil compiler framework. We evaluate our methodology with a set of three different compilers (Intel, Clang and GCC) on two recent generations of Intel multicore platforms. Our results show a good match with the theoretical performance models (i.e. roofline models). We also outperform Pochoir performance by a factor of x2.5 in the best cases.

Abstract: Multi-Processors System-on-Chip (MPSoCs) design is based on the integration of several third-party Intellectual Property (IP) cores. Some of those IPs may include Trojans, extra hardware that can be triggered during operation time in order to perform an attack. Network-on-Chip(NoC), the communication IP of MPSoCs, can include Trojans that spy, modify and denial the sensitive communication inside the chip. Previous works address the malicious NoC threat. However, to find secure and efficient solutions is still a challenge. In this work we propose a novel secure network interfaces that implements a tunnel-based protocol that allows the secure exchange of sensitive data, even in the presence of a malicious NoC. We test our technique under several real application and synthetic traffic and attack scenarios and show that it is a secure and efficient solution.

Abstract: The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. Whereas such a processor offers high computational energy efficiency and parallel scalability, developing effective programming models that address the unique architecture features has presented many challenges. We present here a distributed shared memory (DSM) model supported in software transparently using C++ templated meta-programming techniques. The approach offers an extremely simple parallel programming model well suited for the architecture. Initial results are presented that demonstrate the approach and provide insight into the efficiency of the programming model and also the ability of the NoC to support a DSM without explicit control over data movement and localization.

Abstract: The ΣC (pronounced “Sigma-C”) language was initially designed for Kalray’s MPPA embedded many-core processor. Nonetheless, it was imagined as a target independent language based on C and allowing the Cyclo-Static Data-Flow (CSDF) model of computation. Until now, it was only available for the first generation of the MPPA chip. In this paper, we show how we built an OpenMP back-end for the ΣC language, and we used this compiler to evaluate some of the assets of stream programming and some limitations of the current implementation, by evaluating the performance on several benchmark programs. This new back-end could open the way to utilize this language to study embedded stream programming concepts or to program HPC applications.